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| Ordering number : EN*A1229A CMOS IC LE25FW403A Overview 4M-bit (512Kx8) Serial Flash Memory 30MHz SPI Bus The LE25FW403A is an onboard programmable flash memory device with a 512Kx8-bit configuration. It uses a single 3.0V power supply and supports the serial interface. It has three erase functions depending on the size of memory area in which the data is to be erased: the chip erase function, the sector (64K bytes) erase function, and a page (256 bytes) erase function. A page program method is supported for data writing and it can program any amount of data from 1 to 256 bytes. The page program time depends on the number of bytes programmed and the IC provides a high-speed program time of 1.5ms (typ) when programming 256 bytes at one time. Moreover, equipped with a page write function that allows anywhere from 1 to 256 bytes of data in a page to be rewritten, this device is optimal for applications that perform smallscale rewriting. Features * Read/write operations enabled by single 3.0V power supply: 2.7 to 3.6V supply voltage range * Operating frequency : 30MHz * Temperature range : 0 to 70C * Serial interface : SPI mode 0, mode 3 supported * Sector size : 256 bytes/page sector, 64K bytes/sector * Page erase, sector erase, chip erase functions * Page program function (1 to 256 bytes/page), Page write function (1 to 256 bytes/page) * Hardware protect function (lower 256 pages) * Hardware reset function Continued on next page. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. 70208 SY IM No.A1229-1/18 LE25FW403A Continued from preceding page. * Highly reliable read/write Number of rewrite times : 105 times Page erase time : 10ms (typ.), 20ms (max.), Number of rewrite times: 104 times or less : 25ms (typ.), 300ms (max.), Number of rewrite times: 105 times or less Sector erase time : 30ms (typ.), 500ms (max.) Chip erase time : 300ms (typ.), 5s (max.) Page program time : 1.5ms/256 bytes (typ.), 2.5ms/256 bytes (max.) Page write time : 11ms (typ.), 22.5ms (max.), Number of rewrite times: 104 times or less : 25ms (typ.), 300ms (max.), Number of rewrite times: 105 times or less * Status functions Ready/busy information * Data retention period : 20 years * Package : LE25FW403ATT MSOP8 (225mil) Package Dimensions unit:mm (typ) 3276 5.2 8 5 4.4 6.3 1 (0.7) 1.27 4 0.35 0.85max 0.125 SANYO : MSOP8(225mil) Figure 1 Pin Assignment 0.08 (0.65) 0.5 SI SCK RESET CS 1 2 3 4 Top view 8 7 6 5 SO VSS VDD WP No.A1229-2/18 LE25FW403A Figure 2 Block Diagram ADDRESS BUFFERS & LATCHES XDECODER 4M Bit Flash EEPROM Cell Array Y-DECODER CONTROL LOGIC I/O BUFFERS & DATA LATCHES SERIAL INTERFACE CS SCK SI SO WP RESET Table 1 Pin Description Symbol SCK Pin Name Serial clock This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI SO CS WP RESET VDD VSS Serial data input Serial data output Chip select Write protect RESET Power supply Ground The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. Lower 256 pages are protected when the logic level of this pin is low. The device resets when the logic level of this pin is low. However, reset is disabled when write (erase, program, or page write) are being internally executed by the device. This pin supplies the 2.7 to 3.6V supply voltage. Description No.A1229-3/18 LE25FW403A Table 2 Command Settings Command Read 1st bus cycle 03h 0Bh Page erase Sector erase Chip erase Page program Page write Write enable Write disable Power down Status register read Read silicon ID Exit power down mode DBh D8h C7h 02h 0Ah 06h 04h B9h 05h 9Fh *2 ABh A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 PD *1 PD *1 PD *1 PD *1 PD *1 PD *1 2nd bus cycle A23-A16 A23-A16 A23-A16 A23-A16 3rd bus cycle A15-A8 A15-A8 A15-A8 X 4th bus cycle A7-A0 A7-A0 X X X 5th bus cycle 6th bus cycle Nth bus cycle Explanatory notes for Table 2 X = don't care, h = Hexadecimal notation, A23-A19 = don't care for all commands Even if CS is raised for longer than the bus cycle given in the command settings table, the command will be recognized. However, CS must be raised between one bus cycle and the next. *1. PD: Program data. Input any number of bytes of data from 1 to 256 bytes in 1-byte units. *2. After the first bus cycle, Silicon ID repeatedly outputs 62h (manufacturer code), 11h (device code), and 00h (dummy code). Device Operation The LE25FW403A features electrical on-chip erase functions using a single 3.0V power supply, that have been added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by incorporating the command registers inside the chip. The read, erase, program and other required functions of the device are executed through the command registers. The command addresses and data are latched for program, erase and write operations. Figures 3 and 4 show the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are introduced internally starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon ID. The LE25FW403A supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 3 Serial Input Timing tCPH CS tCLS SCK tCSS tCLHI tCLLO tCSH tCLH tDS SI tDH DATA VALID SO High Impedance High Impedance SPI Mode definition * SPI mode 0: SCK is low logic level when CS falls * SPI mode 3: SCK is high logic level when CS falls No.A1229-4/18 LE25FW403A Figure 4 Serial Output Timing CS SCK tCLZ SO tHO DATA VALID tV SI tCHZ Command Definition "Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below. 1. Read Figure 5 shows the read timing waveforms. There are two read commands, the 4 bus cycle read and 5 bus cycle read. Consisting of the first through fourth bus cycles, the 4 bus cycle read inputs the 24-bit address following (03h) and the data in the designated address is output synchronized to SCK. The data is output on the falling clock edge of fourth bus cycle bit 0. Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output using the falling clock edge of fifth bus cycle bit 0. The only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. While SCK is being input, the address is automatically incremented inside the device and the corresponding data is output in sequence. If the SCK input is continued after the data up to the highest address (7FFFFh) is output, the internal address returns to the lowest address (00000h) and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin is in a high-impedance state. Figure 5: Read 4 Bus Read CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 40 47 8CLK SI 03h Add. Add. Add. N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB No.A1229-5/18 LE25FW403A 5 Bus Read CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 40 47 48 55 8CLK SI 0Bh Add. Add. Add. X N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB 2. Status Registers Device status can be detected using status registers. Table 3 gives the contents of status registers. Table 3 Status Registers Bit Bit0 Name RDY Logic 0 1 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 WEN 0 1 0 0 0 0 0 0 Function Ready Erase/Program/Write Write disabled Write enabled Reserved bits Reserved bits Reserved bits Reserved bits Reserved bits Reserved bits 0 0 0 0 0 0 0 Power-on Time Information 0 2-1. Status Register Read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. * Page erase * Sector erase * Chip erase * Page program * Page write Figure 6 shows the timing waveforms of the status register read. Consisting only of the first bus cycle, the status register read command outputs the contents of the status register from bit 7 synchronized to the falling edge of the clock (SCK) when (05h) is input. If the clock (SCK) is continued after data up to RDY (bit 0) are output, the data is output by returning to the bit 7. Data is output from the falling clock of the first bus cycle bit 0. No.A1229-6/18 LE25FW403A Figure 6 Status Register Read CS Mode3 SCK Mode0 012345678 15 16 23 8CLK SI 05h SO High Impedance DATA MSB DATA MSB DATA MSB RDY (bit 0) The RDY register is for detecting the write (program, erase and page write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. * At power-on * Upon completion of page erase, sector erase or chip erase * Upon completion of page program * Upon completion of page write * After hardware reset operations * If a write operation has not been performed inside the LE25FW403A because, for instance, the command input for any of the write operations (page erase, sector erase, chip erase, page program, or page write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. Bit2, Bit3, Bit4, Bit5, Bit6, Bit7 These are reserved bits. 3. Write Enable Write enable command sets the status register WEN to "1." The write enable command must be issued before performing any of the operations listed below. * Page erase * Sector erase * Chip erase * Page program * Page write Figure 7 shows the timing waveforms. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). No.A1229-7/18 LE25FW403A 4. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. Figure 8 shows the timing waveforms when the write disable operation is performed. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). To exit write disable status (WEN = 0), set WEN to 1 using the write enable command (06h). Figure 7 Write Enable CS CS Figure 8 Write Disable Mode3 SCK Mode0 01234567 SCK 8CLK Mode3 Mode0 01234567 8CLK SI 04h SI 06h High Impedance SO SO High Impedance 5. Power-down The power-down command sets all the commands, with the exception of the command to exit from power-down, to the acceptance prohibited state (power-down). Figure 9 shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). The power-down state is exited using the power-down exit command. Figure 10 shows the timing waveforms of the power-down exit command. The power-down exit command consists only of the first bus cycle, and it is initiated by inputting (ABh). Power-down state is exited also when power is tuned off or when hardware reset is performed. Figure 9 Power-down Figure 10 Exiting from Power-down Power down mode CS Mode3 SCK Mode0 8CLK SI B9h SI CS tPRB 01234567 SCK Mode3 Mode0 8CLK ABh 01234567 High Impedance SO SO High Impedance No.A1229-8/18 LE25FW403A 6. Page Erase Page erase operation sets the memory cell data in any pages to "1." A page consists of 256 bytes. Figure 11 shows the timing waveforms, and Figure 21 shows a page erase flowchart. The page erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (DBh). Addresses A18 to A8 are valid, and all others are "don't care." After the command has been input, the erase operation starts from the rising edge of CS, and it ends automatically under the control of internal timer. Also, end of erase operation can be detected using status register. Page erase time depends on the number of rewrites performed. The page erase time is 10ms (typ)/20ms (max) for up to 104 rewrites, and 25ms (typ)/300ms (max) for up to 105 rewrites. Figure 11 Page Erase Self-timed Erase Cycle tPE CS Mode3 SCK Mode0 012345678 15 16 23 24 31 8CLK SI DBh Add. Add. X High Impedance SO 7. Sector Erase Sector erase operation sets the memory cell data in any sectors to "1." A sector consists of 64K bytes. Figure 12 shows the timing waveforms, and Figure 21 shows an erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A18 and A16 are valid, and all others are "don't care." After the command has been input, the erase operation starts from the rising edge of CS, and it ends automatically under the control of internal timer. Also, end of erase operation can be detected using status register. Sector erase time is 30ms (typ)/500ms (max). If the lower 256 pages are being protected by setting the WP pin to low logic level, the sector erase operation cannot be performed on sectors including the lower 256 pages. Figure 12 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK Mode0 012345678 15 16 23 24 31 8CLK SI D8h Add. Add. X High Impedance SO No.A1229-9/18 LE25FW403A 8. Chip Erase Chip erase operation sets the memory cell data in all the sectors to "1." Figure 13 shows the timing waveforms, and Figure 21 shows an erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (C7h). After the command has been input, the erase operation starts from the rising edge of CS, and it ends automatically under the control of internal timer. Also, end of erase operation can be detected using status register. Chip erase time is 300ms (typ)/5s (max). If the lower 256 pages are being protected by setting the WP pin to low logic level, the chip erase operation cannot be performed. Figure 13 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK Mode0 01234567 8CLK SI C7h High Impedance SO 9. Page Program Page program operation can be used to program any number of bytes from 1 to 256 bytes for the erased pages (page addresses: A18 to A8). Figure 14 shows the timing waveforms, and Figure 22 shows a program flowchart. After CS is set low, the command code (02H) is input followed by the 24-bit addresses. Addresses A18 to A0 are valid. After this, the program data can be loaded until CS rises. If the loaded data exceeds 256 bytes, the 256 bytes loaded last are programmed. Also, if the address of data being loaded reaches the last address of a page (A7 to A0: FFh), the device returns to the start address of the same page (A7 to A0: 00h). Program data must be loaded in 1-byte units. The program operation is not performed if data is loaded in less than byte units and CS is set high. The page program time depends on the number of bytes programmed. When programming 256 bytes, the page program time is 1.5ms (typ)/2.5ms (max). Figure 14 Page Program Self-timed Program Cycle tPP CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 40 47 2079 8CLK SI 02h Add. Add. Add. PD PD PD High Impedance SO No.A1229-10/18 LE25FW403A 10. Page Write Page write operation can be used to rewrite any number of bytes of data from 1 to 256 bytes in a page (page addresses: A18 to A8) without executing erase operation beforehand. Figure 15 shows the timing waveforms, and Figure 23 shows a flowchart. After CS is set low, the command code (0AH) is input followed by the 24-bit addresses. Addresses A18 to A0 are valid. After this, re-write data can be loaded until CS rises. If loaded data exceeds 256 bytes, the 256 bytes loaded last are programmed. If the loaded data is less than 256 bytes, data not loaded on the same page is not rewritten. In addition, if the address of data being loaded reaches the last address of a page (A7 to A0: FFh), the device returns to the start address of the same page (A7 to A0: 00h). Rewrite data must be loaded in 1-byte units. The rewrite operation is not performed if data is loaded in less than byte units and CS is set high. The page write time depends on the number of rewrites. The page write time is 11ms (typ)/22.5ms (max) for up to 104 rewrites, or 25ms (typ)/300ms (max) for up to 105 rewrites. Figure 15 Page Write Self-timed Write Cycle tPW CS Mode3 SCK Mode0 012345678 15 16 23 24 32 39 40 47 2079 8CLK SI 0Ah Add. Add. Add. PD PD PD High Impedance SO 11. Silicon ID Read Silicon ID read allows manufacturer code and device code information to be read. Figure 16 shows the timing waveforms, and Table 6 gives the silicon ID codes. Table 6 Silicon ID Codes Output Code Manufacturer code Device code Dummy code 62h 11h 00h The silicon ID read command consists of only the first bus cycle. If (9Fh) is input, the manufacturer code 62h, device code 11h, and dummy code 00h are output in synchronization with the falling edge of SCK. If SCK input continues, the IC repeatedly outputs the data described above. Data output is performed from the falling edge of clock at the first bus cycle, bit 0. Silicon ID read is terminated by making CS go to high logic level. The silicon ID read command is not accepted during write operations. No.A1229-11/18 LE25FW403A Figure 16 Silicon ID Read CS Mode3 SCK Mode0 012345678 15 16 23 31 8CLK SI 9Fh N SO High Impedance 62h MSB N+1 11h MSB N+2 00h MSB 12. Hardware Reset A hardware reset can be performed by setting the RESET pin to low logic level. Figure 17 shows the timing waveforms. The hardware reset is disabled while write operation (erase, program, or page write) is being executed in the device. The pin SO is held in the high-impedance state while the device is in the reset mode. Figure 17 Hardware Reset tRES CS tHRB tRP RESET 13. Hardware Data Protection Lower 256 pages can be protected by setting the WP pin to low logic level. Figure 18 shows the timing waveforms. In addition, the device has an internal power on reset function to prevent unintentional write operations at power on. Figure 18 Write Protection CS tWPS WP tWPH SCK SI SO High Impedance High Impedance No.A1229-12/18 LE25FW403A In order to protect against unintentional writing at power-on, the LE25FW403A incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 19 Power-down Timing VDD VDD(max) Program, Erase and Write Command not Allowed No Device Access Allowed VDD(min) tPU_READ tPU_WRITE tPD 0V vBOT 14. Software Data Protection The LE25FW403A eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. * When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) * When the page program and page write data is not in 1-byte increments 15. Power On VDD is applied to CS at power on to prevent unintentional write operations. To start read operations, turn the power on and input a command 100s (tPU_READ) after the power supply voltage has reached 2.7V or higher and has been stabilized. In addition, to start write operations, turn the power on and input a command 10ms (tPU_WRITE) after power supply voltage has reached 2.7V or higher and has been stabilized. Figure 20 Power On Timing Program, Erase and Write Command not Allowed VDD VDD(max) Full Access Allowed Chip selection not Allowed Read Access Allowed VDD(min) tPU_READ tPU_WRITE 0V 16. Decoupling Capacitor A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. No.A1229-13/18 LE25FW403A Specifications Absolute Maximum Ratings Parameter Maximum supply voltage DC voltage (all pins) Storage temperature Tstg Symbol With respect to VSS With respect to VSS Conditions Ratings -0.5 to +4.6 -0.5 to VDD+0.5 -55 to +150 unit V V C Operating Conditions Parameter Operating supply voltage Operating ambient temperature Symbol Conditions Ratings 2.7 to 3.6 0 to 70 unit V C Allowable DC Operating Conditions Parameter Read mode operating current Symbol ICCR Conditions min CS=0.1VDD, RESET=WP=0.9VDD SI=0.1VDD/0.9VDD, SO=open, Operating frequency=30MHz, VDD=VDD max Write mode operating current CMOS standby current ICCW ISB VDD=VDD max CS=RESET=WP=VDD-0.3V, SI=VSS/VDD, SO=open, VDD=VDD max Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage ILI ILO VIL VIH VOL VIN=VSS to VDD, VDD=VDD max VIN=VSS to VDD, VDD=VDD max VDD=VDD max VDD=VDD min IOL=100A, VDD=VDD min IOL=1.6mA, VDD=VDD min Output high voltage VOH IOH=-100A, VDD=VDD min VDD-0.2 -0.3 0.7VDD 2 2 0.3VDD VDD+0.3 0.2 0.4 V A A V V V 15 mA A Ratings typ max unit 6 mA 10 Power-on Timing Parameter Time from power-on to read operation Time from power-on to write operation Power-down time Power-down voltage tPU_READ tPU_WRITE tPD vBOT Symbol min 100 10 10 0.2 Ratings max s ms ms V unit Pin Capacitance at Ta=25C, f=1MHz Parameter Output pin capacitance Input pin Capacitance Symbol CDQ CIN VDQ=0V VIN=0V Conditions max 12 6 unit pF pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. No.A1229-14/18 LE25FW403A AC Characteristics Parameter Clock frequency Input signal rising/falling time CS setup time CS hold time CS wait pulse width Output high impedance time from CS Data setup time Data hold time SCK setup time SCK hold time SCK logic high level pulse width SCK logic low level pulse width Output low impedance time from SCK Output data time from SCK Output data hold time Page erase cycle time Number of rewrite times: 104 times or less Number of rewrite times: 105 times or less tSE tCHE tPP Symbol min fCLK tRF tCSS tCSH tCPH tCHZ tDS tDH tCLS tCLH tCLHI tCLLO tCLZ tV tHO tPE 0 10 25 30 0.3 1.5 0.04+ n*1.46/256 Page write cycle time WP setup time WP hold time Reset setup time Reset pulse width Hardware reset recovery time Power-down recovery time Number of rewrite times: 104 times or less Number of rewrite times: 105 times or less tWPS tWPH tRES tRP tHRB tPRB 50 50 10 100 1 25 tPW 11 25 22.5 300 ms ms ns ns ns ns s ns 2.5 ms 20 300 500 5 5 5 10 10 16 16 0 8 15 10 10 25 15 Ratings typ max 30 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms s unit Sector erase cycle time Chip erase cycle time Page programming cycle time (256 bytes) Page programming cycle time (n bytes) AC Test Conditions Input pulse level******************** 0V, 3.0V Input rising/falling time********* 5ns Input/Output timing level****** High data: 2.0V, Low data: 0.8V Output load *************************** 30pF Note: As the test conditions for "typ", the measurements are conducted using 3.0V for VDD at room temperature. No.A1229-15/18 LE25FW403A Figure 21 Erase Flowchart Page/sector erase Chip erase Start Start 06h 06h Write enable Write enable C7h DBh/D8h Set chip erase command Address 1 Set page erase and small sector erase command Start erase on rising edge of CS Address 2 05h Dummy Set status register read command Start erase on rising edge of CS Bit 0 = "0" ? YES Set status register read command NO 05h End of erase NO Bit 0 = "0" ? YES * Automatically placed in write disabled state at the end of the erase End of erase * Automatically placed in write disabled state at the end of the erase No.A1229-16/18 LE25FW403A Figure 22 Program Flowchart Figure 23 Page Write Flowchart Start Start 06h Write enable 06h Write enable 02h Set page program command 0Ah Set page program command Address 1 Address 1 Address 2 Address 2 Address 3 Address 3 Program data 0 Rewrite data 0 Program data n Rewrite data n Start program on rising edge of CS Start program on rising edge of CS 05h Set status register read command 05h Set status register read command NO Bit 0= "0" ? YES NO Bit 0= "0" ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. End of programming * Automatically placed in write disabled state at the end of the programming operation. No.A1229-17/18 LE25FW403A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2008. Specifications and information herein are subject to change without notice. PS No.A1229-18/18 |
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